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Dual Channel, 14-Bit, 10 MSPS A/D Converter with Analog Input Signal Conditioning AD10410
PRELIMINARY TECHNICAL DATA
For current information contact (336) 605-4385
PERFORMANCE FEATURES
Dual, 10 MSPS minimum sample rate - Channel-channel matching, +/- .1% gain error - Channel-channel isolation, >80dB - DC-Coupled Signal conditioning included Selectable Bipolar Input Voltage Range (+/- 0.5V, +/- 1.0V, +/- 2.0V) Gain flatness up to Nyquist: < 0.2dB 85dB Spurious-Free Dynamic Range Straight binary output format 3.3 / 5V CMOS-Compatible Output Levels .75W Per Channel Industrial and Military Grade
APPLICATIONS Phased Array Receivers Communications Receivers FLIR Processing Secure Communications GPS Anti-Jamming Receivers Multichannel, Multimode Receivers
amplifier. The AD9240s have on-chip track-and- hold cirucutry and utilize an innovative multipass architecture to achieve 14-bit, 10MSPS performance. The AD10410 uses innovative highdensity circuit design and laser-trimmed thin-film resistor networks to achieve exceptional matching and performance while still maintaining excellent isolation, and providing for significant board area savings. The AD10410 operates with +/- 5.0V for the Analog signal conditioning with a separate +5.0V/3.3V supply for the digital output phase. Each channel is completely independent allowing operation with independent Encode and Analog Inputs. The AD10410 also offers the user a choice of Analog Input Signal ranges to further minimize additional external signal conditioning, while still remaining general-purpose. The AD10410 is packaged in a 68-lead Ceramic Gull Wing Package, footprint compatible with the earlier generation AD10242 (12-bit, 40 MSPS) and AD10265 (12-bit, 65MSPS). Manufacturing is done on Analog Devices, Inc. Mil-38534 Qualified Manufacturers Line (QML) and components are available up to Class-H (-55 to 125C).
PRODUCT DESCRIPTION
The AD10410 is a full channel ADC solution with on-module signal conditioning for improved dynamic performance and fully matched channel-to-channel performance. The module includes two wide dynamic range AD9240 ADCs. Each AD9240 has a dc-coupled amplifier front end including a low distortion, high bandwidth amplifier, providing a high input impedance and gain, and driving a single to differential
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate of 10 MSPS. 2. Input amplitude options, user configurable. 3. Input signal conditioning included; both channels matched for gain. 4. Fully tested/characterized performance for full channel. 5. Footprint compatible family; 68-pin LCC.
FUNCTIONAL BLOCK DIAGRAM
Rev. Pr A This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.
TARGET SPECIFICATIONS
Electrical Characteristics (AVCC=5V; AVEE=-5V; DVCC=+3.3V applies to each ADC unless otherwise noted Parameter RESOLUTION DC ACCURACY No Missing Codes Offset Error Offset Error Channel Match Gain Error1 Gain Error Channel Match ANALOG INPUT (AIN) Input Voltage Range AIN1 AIN2 AIN3 Input Resistance AIN1 AIN2 AIN3 Input Capacitance2 Analog Input Bandwidth3 ENCODE INPUT4,5 High Level Input Voltage Low Level Input Voltage High Level Input Current (VIN) = (AVCC) Low Level Input Current (VIN) = (0 V) Input Capacitance SWITCHING PERFORMANCE Maximum Conversion Rate6 Minimum Conversion Rate6 Aperture Delay (tA) Aperture Delay Matching Aperture Uncertainty (Jitter) ENCODE Pulse With High ENCODE Pulse With Low Output Delay (tOD) SNR Analog Input @ 1MHz Analog Input @ 5MHz Temp Test Level Mil SubGroup Min
AD10410
AD10410BZ/QML-H Typ 14 Max Units Bits
Full +25C Full Full +25C Full Full
VI I VI V I VI V
1,2,3 1 2.3 1 2,3
Guaranteed 2.2 2.2 0.1 0.5 0.8 0.1
%FS %FS % %FS %FS %
Full Full Full Full Full Full +25C Full
I I I IV IV IV IV V
1,2,3 1,2,3 1,2,3 12 12 12 12 99 198 396 0
0.5 1.0 2 100 200 400 4.0 30 101 202 404 7.0
V V V pF MHz
Full Full Full Full
I I I I
1,2,3 1,2,3 1,3,3 1,2,3
+3.5 +1.0 10 10 5
V V pF
Full Full +25C +25C +25C +25C +25C Full
VI V V V V IV IV IV
4,5,6 12
10 TBD TBD 0.3
12 12 12
TBD
MSPS MSPS MSPS ns ps rms ns ns ns
+25C Full
V II
4 5,6
73 73
dB dB
SINAD8 Analog Input @ 1MHz Analog Input @ 5MHz
+25C Full
V II
4 5,6
70 70
dB dB
Rev. Pr A This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.
TARGET SPECIFICATIONS
Electrical Characteristics (AVCC=5V; AVEE=-5V; DVCC=+3.3V applies to each ADC unless otherwise noted) Parameter Temp Test Level Mil SubGroup Min
AD10410
AD10410BZ/QML-H Typ Max Units
SPURIOUS-FREE DYNAMIC RANGE9 Analog Input @ 1MHz Analog Input @ 5MHz
+25C Full
V II
4 5,6
85 85
dBFS dBFS
Two-tone IMD Rejection10 FI, F2@ -7 dBFS CHANNEL-TO-CHANNEL ISOLATION11 TRANSIENT RESPONSE LINEARITY Differential Non-Linearity (Encode = 20MHz) Intergal Nonlinearity (Encode = 20MHz) OVERVOLTAGE RECOVERY TIME12 VIN = 2.0 x FS VIN = 4.0 x FS DIGITAL OUTPUTS High Level Output Voltage (IOH) = 50) Low Level Output Voltage (IOH) = 0.5mA) High Level Output Voltage (IOL) = 1.6mA) Low Level Output Voltage (IOL) = 50) Output Capacitance
Full +25C +25C
II IV V
4,5,6 12 80dB TBD
-80
dBFS dB nS
+25C Full +25C Full
IV IV V V
12 12
TBD TBD TBD TBD
LSB LSB LSB LSB
Full Full
IV IV
12 12
TBD TBD
nS nS
Full Full Full Full
I I I I
1,2,3 1,2,3 1,3,3 1,2,3
+4.5 +2.4 +0.4 +0.1 5
V V V V pF
POWER SUPPLY AVCC Supply Voltage I (AVCC) Current AVEE Supply Voltage I (AVEE) Current DVCC Supply Voltage I (DVCC) Current ICC (Total) Supply Current Power Dissipation (Total) Power Supply Rjection Ratio (PSRR) Pass Band Ripple to 10MHz
Full Full Full Full Full Full Full Full Full
VI V VI V VI V I I I IV
4.75
3.0 1,2,3 1,2,3 7,8 12
+5.0 TBD -5.0 TBD 3.3V TBD TBD 1.5
5.25
V mA V
mA
5.25 V mA mA W
%FSR/%Vs
0.02 0.2
dB
Rev. Pr A This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.
TARGET SPECIFICATIONS
Electrical Characteristics (AVCC=5V; AVEE=-5V; DVCC=+3.3V applies to each ADC unless otherwise noted)
AD10410
NOTES 1. Gain tests are performed on Ain2 input voltage range. 2. Input Capacitance spec. combines AD8037 die capacitance + Ceramic package capacitance. 3. Full Power Bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis is reduced by 3dB. 4. All AC specifications tested by driving single ended ENCODE . 5. ENCODE driven by single-ended source; ENCODE bypassed to ground through .1 F capacitor.; see "Encoding the AD10410" for details. 6. Minimum and Maximum conversion rates allow for variation in Encode Duty Cycle of 50% 5%. 7. Analog Input signal power at -1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonics removed). Encode = 19MSPS. 8. Analog Input signal power at -1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 10MSPS. 9. Analog Input signal power swept from -1 dBFS to -60 dBFS; SFDR is ratio of converter fullscale to worst spur. 10. Both input tones at -7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst 3rd order intermod product. f1=2.5MHz 100kHz, 50kHz f1-f2 300kHz. 11. Channel to Channel Isolation tested with A channel grounded and a Fullscale signal applied to B channel. 12. Input driven to 2x and 4x Ain1 range for > 4 clock cycles. Output recovers inband in specified time with Encode = 10MSPS. 13. Outputs are sourcing TBD A. 14. Outputs are sinking TBD A.
All specifications guaranteed within 100mS of initial power up regardless of sequencing.
TEST LEVEL I II III IV V VI 100% Production Tested 100% Production Tested at +25C, and sample tested at specified temperatures. AC testing done on sample basis Sample Tested only Parameter is guaranteed by design and characterization testing Parameter is a typical value only 100% production tested at temperature at 25C: sample tested at temperature extremes
Rev. Pr A This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.
AD10410
Pin No.
1 2,5,9-11 3 6 7 8 4 12 13 14 26,27 15-25, 31-33 28 29 30 43,44 34-42,45-49 53-54,58-61,65,68 50 51 52 55 57 56 62 63 64 66 67
Name
SHIELD AGNDA VREF_A AINA1 AINA2 AINA3 RANGEA CML-A AVEE AVCC DGNDA D0A-D13A NC ENCODEA DVCC DGNDB D0B-D13B AGNDB DVCC ENCODEB NC VREF-B CML-B RANGEB AINB1 AINB2 AINB3 AVCC AVEE
PIN FUNCTION DESCRIPTIONS Function
Internal Ground Shield between channels A Channel Analog Ground. A and B grounds should be connected as close to the device as possible A Channel Internal Voltage Reference Analog Input for A side ADC (nominally 0.5V) Analog Input for A side ADC (nominally 1.0V) Analog Input for A side ADC (nominally 2.0V)
Analog Negative Supply Voltage (nominally -5.0V) Analog Positive Supply Voltage (nominally +5.0V) A Channel Digital Ground Digital Outputs for ADC A. D0 (LSB) Data conversion initiated on rising edge of ENCODE input Digital Positive Supply Voltage (nominally +5.0V / + 3.3V) B Channel Digital Ground Digital Outputs for ADC B. D0 (LSB) B Channal Analog Ground. A and B grounds should be connected as close to the device as possible Digital Positive Supply Voltage (nominally +5.0V / + 3.3V) Data conversion initiated on rising edge of ENCODE input
B Channel Internal Voltage Reference Analog Input for B side ADC (nominally 0.5V) Analog Input for B side ADC (nominally 1.0V) Analog Input for B side ADC (nominally 2.0V) Analog PositiveSupply Voltage (nominally +5.0V ) Analog Negative Supply Voltage (nominally -5.0V)
PIN CONFIGURATION 68-Lead Leaded Ceramic Chip Carrier
RA NGE A VR EF_A SH IE LD AG NDA AG NDA AG NDA AG NDB AG NDB AG NDB
61
A IN A3
A IN A2
A IN A1
A IN B3
A IN B2
63
9
8
7
6
5
4
3
2
1
68
67
66
65
64
A IN B1
62
AV CC
AV EE
AGNDA
10
PIN 1
60 59 58 57 56 55
AGNDB AG NDB AGNDB C M L-B RA NGE B V R EF _B AG NDB AG NDB NC ENCODEB DV CC D 1 3 B (M S B B ) D1 2B D1 1 B D1 0 B D9 B DG NDB
AGNDA 11 C M L -A AVEE AVCC D 0 A (L S B A ) D1 A D2A D3 A D4 A D5 A D6A D7 A D8 A D9 A D1 0A DGNDA 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A D 10410
T o p V ie w ( N o t t o S c a le )
54 53 52 51 50 49 48 47 46 45 44
D6 B
D7 B
D1 3A (MS BA )
DG ND A
D0B ( LS BB )
EN CO DEA
PLANNED GRADES
Model AD10410BZ SMD/QML-H AD10410/PCB Temperature Range -40C to 85C (Case) -55C to 125C (Case) Package Description 68-pin Leaded Ceramic Chip Carrier 68-pin Leaded Ceramic Chip Carrier Evaluation Board with AD10410BZ
DG ND B
D3 B
D1 2A
D1 B
D1 1 A
D2 B
D4 B
DV CC
D5 B
D8 B
NC
Rev. Pr A
This information applies to a product which is in development. Specifications are subject to change without notice. Contact factory for most recent information. Analog Devices Sensitive Material - not to be reproduced or distributed without permission.

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